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MELP Coding Questions

From: Jeff Brower <>
Subject: Re: MELP coding questions
To: Matthieu 


>1) About the SigSD4 Audio Module.
>We already had the documentation you sent.
>It was in SigC54xx Dev System and Algorithm IDE, p3 and p4.
>The SigSD4 Audio module will be plugged in our hardware
>to be sure that the MELP is working. The Audio Module
>is here on debug purpose, to be sure that everything is working
>To do this, we need the pineout of the 72 points Sodimm module.
>Otherwise, what will be the interest of the Audio Module ?

The pin-out of the Audio Module is the same as the processor module.  If you 
have edge connector definition for one module, you have it for all modules.  
This allows the modules to be used in a "bus" configuration; i.e. the module 
positions are interchangeable.

I think we have explained this before.

>2) About the MELP algorithm.
>Our main concern is to have it working. Everything seems to work
>on your board, when doing simulation.
>But we need to know the format of the frame.
>- How to define channels in the frame ? 

Please explain this question in more detail.

>- What is the size of one channel ( number of bits per channels )?

On analog side, 16-bits per sample, 180 samples per frame.  On digital side, 54 
bits per frame (6-bit coefficients).

>When the Melp is running:

>- What should be the bclk: please explain clearly

2400 Hz.  You can use internal C54x counter to derive this value if the DSP is 
to provide the clock (i.e. clock is outut), or use external clock provided by 
interface equipment (i.e. clock is input).  The choice whether clock is 
input/output is made in BSP setup registers.

>- what should be the BFS clock ? ( The sampling frequency ? something else ?)

BCLK divided by 128 is typical; i.e. framesync pulse every 128 clocks.  Again, 
this can be configured to be drived internally (i.e. framesync is output) or 
supplied by external framesync signal (i.e. framesync is input) in the C54x BSP 
set-up registers.  The choice of whether framesync is input/output is made in 
BSP setup registers.

>How the Melp is outputing the 54 bits of a MELP frame ?
>- by 6 bits packets ? in another way ?

Yes, 6-bits per coefficient.  Each 16-bit word in the "chbuf" array (see 
melp_rt.c) has a coefficient (upper 10 bits not used).  After each frame is 
complete, there are nine (9) valid coefficients in the chbuf array.

>We need to know the place of the bits , how this is working.

See comments above.

>Since the SigC54xx is supposed to be able of fully processing and MELP-encoding 
>up to 
>six full-duplex channels at 8 kHz sampling rate, you certainly had developped a 
>and channel format.

Three (3) full-duplex channels, one per processor, or six (6) half-duplex 

>For our system, we will be working with four time slots.

Do you mean four (4) Rx time slots and (4) Tx time slots (4 full-duplex 
channels), or four (4) Rx *either or* Tx time slots?

I suggest that you send to us a system diagram, and show the data flow that you 
need.  This can avoid confusion that might result if use different terminology 
to describe the similar things.

>But once again, we do not know how to design our frame due to the lack of 
>about the Melp. One of the time slot will be used to do analysis, one of the 
>other to do synthesis.

Ok, this means a time slot is half-duplex.  Is that true for all 4x time slots 
in your system definition?

>We want to know how to fill those time slots

You absolutely must become familiar with BSP (buffered serial port) 
configuration and setup registers.  There is not a way to avoid this.  Do you 
have the books:

  "TMS320C54x DSP, CPU and Peripherals"  (Reference Set, Volume 1)

  "TMS320C54x DSP, Enhanced Peripherals"  (Reference Set, Volume 5)

The first one covers C549 and BSP ports.  The second one is for reference only, 
as it covers McBSP ports (not on C549, only on C5402, C5409, C5416, etc).

> and what will be the result of the synthesis.

The synthesis result will be 16-bit samples in the speech_out buffer 
(melp_rt.c).  These can be sent directly to the codec.

>We are working with a 2400 bit/s bit stream. Not 2450 or 2500.
>It is exactly 2400 bit/s.


>About the real time C code:

Where is FRAMESIZE?  There is not a FRAMESIZE in the .c and .h files, as far as 
I know.

FRAME is the analysis framesize, in samples (180); CHSIZE is number of 
coefficients of compressed speech per frame(9); NUM_CH_BITS is valid bits per 
coefficient (6).

Jeff Brower
DSP sw/hw engineer